PDF Ebook The UVM Primer, by Ray Salemi
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The UVM Primer, by Ray Salemi
PDF Ebook The UVM Primer, by Ray Salemi
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The UVM Primer uses simple, runnable code examples, accessible analogies, and an easy-to-read style to introduce you to the foundation of the Universal Verification Methodology. You will learn the basics of object-oriented programming with SystemVerilog and build upon that foundation to learn how to design testbenches using the UVM. Use the UVM Primer to brush up on your UVM knowledge before a job interview to be able to confidently answer questions such as "What is a uvm_agent?" , "How do you use uvm_sequences?", and "When do you use the UVM's factory." The UVM Primer's downloadable code examples give you hands-on experience with real UVM code. Ray Salemi uses online videos (on uvmprimer.com) to walk through the code from each chapter and build your confidence. Read The UVM Primer today and start down the path to the UVM.
- Sales Rank: #445410 in eBooks
- Published on: 2013-10-29
- Released on: 2013-10-29
- Format: Kindle eBook
About the Author
Ray Salemi is a senior verification consultant with Mentor Graphics. Salemi started his career in Electronic Design Automation with Gateway Design Automation, the inventors of Verilog. Since then he has worked for Cadence Design Systems, Sun Microsystems, and several startups. Ray Salemi is the author of the popular introduction to simulation, FPGA SIMULATION.
Most helpful customer reviews
6 of 6 people found the following review helpful.
Excellent intro to UVM
By Kari
This UVM primer fills a large void in learning the basic concepts of UVM. While one can take a class or read articles and code snippets on many of the Verification websites, this book is helpful on getting the overall picture which helps to answer the question "why bother with UVM". I highly recommend the book for anyone new to UVM as well as for those who have been using UVM for a while. In Verification it is easy to get too mired up in the details to forget what where you're going and why. The book is concise, easy to read, and even had me chuckling at times. I've been working as an ASIC Design/Verification Engineer for over a decade, have been using UVM for 2 years, and this is one of the best books I've read on the subject. It's highly recommended.
2 of 2 people found the following review helpful.
Excellent introductory book! If you want to know how to go from a Verilog testbench to SystemVerilog testbench, this is it!
By Ruben Martinez
I had been looking for a book that walked me from a testbench originally written in Verilog and how to evolve it to Systemverilog written in the Universal Verification Methodology (UVM) style. The writing in this primer is easily understood and entertaining. Support is available from the author's website in the form of downloadable SystemVerilog source code from his website. Additional support in the form of videos is also available on Youtube from his channel. To get the most from this book, you should be familiar with Java since SystemVerilog classes and methods are based heavily on Java.
To fill in the necessary gaps, I would recommend "System Verilog for Verification" by Chris Spears as a follow up book.
1 of 1 people found the following review helpful.
Great Primer to start leaning UVM.
By J N
This is a good book to learn the basics of UVM. The author takes a simple Verilog test bench and converts it System Verilog, Object oriented Verilog and then UVM. You can see the evolution of the test bench as it is updated. For best results, download the code and follow along on the You Tube channel. This book will teach the terminology and give you a good overview of UVM.
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